Design of a Ultra Low-Power 2.4GHz System-on-Chip for residential usage

The primary goal of this ultra low-power transceiver IC project is to realize an innovative integrated transceiver front-end. It is designed and developed for low bit rate data transfer for general consumer applications and consumes very little power. Introduction Many applications and Wireless Personal Area Network (WPAN) nodes in the ambient intelligent home of the future would require only low bit-rates (only a few bps up to 1 kbps). LP/LBR (Low power/low bit-rate) RF transceivers require a new architectural approach, compared to moderate and high-speed multi-media wireless link, in order to prolong the battery lifetime and thus minimize battery replacement for the consumers [1]. In the future, it is envisaged that ultra low-power RF transceivers may not need any battery pack, as it can extract all needed energy from the environment, to power up an IC chip for low bit-rate applications. Therefore, this project aims to develop a system-on-chip (SoC) comprising a low-power RF front-end architecture, a FSK/GFSK modem, and an 32-bit microcontroller from Infineon. In order to achieve ultra low-power consumption, the subthreshold design concept will be employed in the RF front-end. In addition, a high level of integration is necessary to reduce the cost of the